Flexible DSP Accelerator using CarrySaveArithmatic
Tiny arithmetic circuit inside Functional Computational Unit of DSP accelerator can affect the complete DSP accelerator performance
Present day applications on signal processing requires a very high degree of computation. For example in the area of multimedia, the information required to present the multimedia data is increasing.This is because of the increased demand of clarity of the multimedia content on desktop and embedded applications.Most of the embedded devices which supports multimedia content like displaying of video data and image data requires large amount of calculations which gave rise to DSP accelerator.
If the embedded application requires handling of HD or 4K content, then it is required to have a powerful DSP which has a very high computational capability on a small hand held device.This gives rise to the need of reduction in power consumption and area of the chip.
The DSP accelerator consists of multiple Flexible computational units which intern consists of amount arithmetic circuits. Again the main base of the arithmetic circuit is adder circuit. So, by modifying the adder circuits of the flexible computational unit, it is possible to reduce the power consumption and area of the DSP accelerator effectively.
So it is required to understand the power consumption and area of various adder circuits.Then simulate them and get the numbers in terms of gate count and uW power dissipation.
We will be sharing the Verilog code for various arithmetic circuits soon.
Present day applications on signal processing requires a very high degree of computation. For example in the area of multimedia, the information required to present the multimedia data is increasing.This is because of the increased demand of clarity of the multimedia content on desktop and embedded applications.Most of the embedded devices which supports multimedia content like displaying of video data and image data requires large amount of calculations which gave rise to DSP accelerator.
If the embedded application requires handling of HD or 4K content, then it is required to have a powerful DSP which has a very high computational capability on a small hand held device.This gives rise to the need of reduction in power consumption and area of the chip.
The DSP accelerator consists of multiple Flexible computational units which intern consists of amount arithmetic circuits. Again the main base of the arithmetic circuit is adder circuit. So, by modifying the adder circuits of the flexible computational unit, it is possible to reduce the power consumption and area of the DSP accelerator effectively.
So it is required to understand the power consumption and area of various adder circuits.Then simulate them and get the numbers in terms of gate count and uW power dissipation.
We will be sharing the Verilog code for various arithmetic circuits soon.
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